1. Technical Field
A method for manufacturing a semiconductor device is disclosed which includes forming multi-level interconnection lines with a dual damascene process.
2. Description of the Related Art
Recently, with increased integration of semiconductor devices, limited results have been achieved in connection with decreasing line widths using photolithography processes. To solve the above-mentioned problem, a damascene process has been used.
Generally, a trench is formed by etching an insulating layer, and a an interconnection line is formed in the trench by a self-aligned dual damascene process.
In the self-aligned dual damascene process, a via connecting the lower and upper interconnection lines is aligned at a bottom of the trench. That is, in the self-aligned dual damascene process, an insulating layer is selectively etched with a photolithography process to form a trench exposing a via at the bottom thereof, and a conductive layer is formed with W, Al or Cu to fill the trench. After that, a portion of the conductive layer outside of the trench, which is not needed, is removed by an etching or a chemical mechanical polishing (CMP) to form an interconnection line in the trench.
The above-mentioned self-aligned dual damascene process is mainly used for forming a bit line, a word line and a metal interconnection line of a dynamic random access memory (DRAM). Specifically, by using a self-aligned dual damascene process for forming a trench, a via hole that is used to form a via connecting upper and lower interconnection lines, may be formed simultaneously. By using the self-aligned dual damascene process, a height difference due to the interconnection lines is not generated, since the via and interconnection lines are buried in the interlayer insulating layers.
FIGS. 1A to 1D are cross-sectional views illustrating a conventional method for forming a multi-level metal interconnection line according to a conventional self-align dual damascene process.
Referring to FIG. 1A, interlayer insulating layers 12 and 13 and an etching stop layer 14 are formed on a semiconductor substrate 11. After that, the etching stop layer 14 and the interlayer insulating layer 13 are selectively etched to expose an area where a first metal interconnection line is to be formed.
Subsequently, a metal layer is deposited on the exposed area and selectively removed to form a metal interconnection line 15 in the etching stop layer 14 and the interlayer insulating layer 13.
Referring to FIG. 1B, a third interlayer insulating layer 16 is formed on the etching stop layer 14 and the metal interconnection line 15. An etching stop layer 17 and a fourth interlayer insulating layer 18 are successively formed on the third interlayer insulating layer 16, and a photoresist layer (not shown) is formed on the fourth interlayer insulating layer 18, then a via hole mask (not shown) is formed by exposing and developing the photoresist layer.
Subsequently, the fourth interlayer insulating layer 18, the etching stop layer 17 and the third insulating layer 16 are etched using the via hole mask to form a via hole 19, which exposes a predetermined surface of the metal interconnection line 15.
Then, after removing the via hole mask, a photoresist layer is formed on the fourth interlayer insulating layer 18 in which the via hole 19 is formed and a trench mask 20, exposing a larger area than the via hole 19, is formed by exposing and developing the photoresist layer.
Referring to FIG. 1C, a trench 21 is formed by etching the fourth interlayer insulating layer 18 using the trench mask 20. When the trench 21 is formed, the etching is stopped by the etching stop layer 17.
Referring to FIG. 1D, after removing the trench mask 20, a metal layer is deposited on the resulting structure, then an etch back or a chemical mechanical polishing (CMP) is carried out until the surface of the fourth interlayer insulating layer 18 is exposed, and thereby to form a metal interconnection line 22 in the trench 20. When the metal interconnection line 22 is formed, a via 22a connected to the metal interconnection line 15 is formed in the via hole.
As shown in FIG. 2A, after forming the trench by etching the fourth interlayer insulating layer 18, the etching stop layer 17 remains intact except at the via hole region. The etching stop layer 17 is usually formed with a nitride layer having a high capacitance value, which in this case, results in a problem of a capacitance increase due to the remaining etching stop layer 17.
Also, as shown in FIG. 2B, when the thicknesses of insulating layers are increased, the etch profile on the corner (A) of the trench may be distorted due to the low etch selectivity between the insulating layers formed with the oxide layers and the etching stop layer formed with the nitride layer.